1. Technical Field
Embodiments of the present disclosure relate generally to phase-locked loops (PLL) and delay-locked loops (DLL), and more specifically to techniques for correcting for offset errors in a PLL/DLL.
2. Related Art
A PLL is generally a circuit that receives a reference clock as an input, and generates an output clock aligned in phase with respect to the reference clock. The frequency of the output clock may be equal to or a multiple of the frequency of the reference clock. A DLL is generally a circuit that generates an output clock aligned in phase with respect to a reference clock, with the output clock typically having a same frequency as that of the reference clock.
An offset error is said to be present in a PLL/DLL when, in the locked state, there exists a non-zero phase difference between the corresponding reference clock and the output clock of the PLL/DLL. A locked state of a PLL/DLL refers to a condition when the PLL/DLL is operating in the steady state, in which the respective phases of the reference clock and output clock are (or should be) ideally aligned with respect to each other, i.e., the phase difference between the reference clock and the output clock should be zero. However, even in such locked/steady state, due to various conditions, a non-zero phase difference may be present.
Embodiments of the present disclosure are directed to correcting for offset-errors in a PLL/DLL.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.